Design considerations for 500W Class D automotive subwoofer amplifiers
Class D designs promise higher output power within a given automotive electronics system volume. But converting to a Class D from a Class AB amp is challenging because the modes of operation are significantly different and ccuit protection schemes must also be adapted for the different topologies.
By Johan Strydom and Jun Honda, International Rectifier

In audio applications there is a trend towards Class D audio amplifiers as replacements for traditional Class AB electronics. The main driving forces are improved efficiency and space savings. Converting to Class D designs promises higher output power within the same system volume or miniaturization at existing power levels-both desirable for automotive audio and infotainment applications.
Converting to Class D for traditional Class AB amplifier designers can be quite daunting as the modes of operation are significantly different. Moreover, the circuit protection schemes must also be adapted for the different topologies. In an attempt to simplify these issues, the basic design procedure for a 500W, 2Ω automotive Class D subwoofer amplifier is presented here.
The Class D amplifier
The major differences between a Class AB amplifier and a Class D amplifier are tabulated in Table 1 below. It can be seen that the main advantages of Class D amplifiers are efficiency, stability, and inherently low output impedance (voltage source), which are all beneficial for driving speaker loads. (For a more complete discussion on the differences between the Class AB and Class D amplifiers, please refer to Application Note AN-1071 [Reference 1].)

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Design of a Class D amplifier
For the Class D amplifier design shown in Figure 1 above, consider the following requirements, given in Table 2 below. For this design a half bridge topology was chosen, as it tends to be the t cost effective solution if the proportionally higher bus voltage requirements can be met. As can be seen in Figure 1, the supply voltages, active devices, output filter, gate drive, and protection circuits have to be designed.

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Selection of power devices
The first step for selecting the switching devices is to estimate the minimum bus voltage, which is dependent on output voltage swing. In this respect, the design task starts out identical to that for a Class AB amplifier. Considering the power requirement is for 1% THD (Total Harmonic Distortion), the required peak-to-peak voltage swing (without clipping) at full load is given by Equation 1:

where M is the maximum modulation index. For this design, a modulation index of 100% is possible. Thus neglecting supply regulation and device on-resistance, the minimum bus voltages (+B or "B) for a half bridge topology will each be half of the peak-to-peak voltage swing in Equation 1 above.
As with other hard switching converters, the voltage rating of the switching devices should be on the order of 50% higher than the overall bus voltage to allow for power supply fluctuations and peak turn-off voltage. The peak load current (thus peak switching device current) is given by Equation 2:

To determine the design parameters of the switching device, the switching frequency also needs to be known. Establishing the optimum frequency can be a complicated task. First, the switching (carrier) frequency should be at least 10 times higher than the required bandwidth of the amplifier or (THD) deterioration at the high end of the audible frequency spectrum will occur. For a full bandwidth (20 kHz and above) amplifier, this typically means a switching frequency around 400 kHz. The higher the switching frequency, the smaller the low pass output filter, because the filter corner frequency is shifted higher.
As the switching frequency increases, the amplifier efficiency will drop due to the switching loss increases. Furthermore, the finite switching time will become a larger portion of the overall switching period. This will affect the "square-ness" of the carrier, which will impact the THD of the amplifier. Thus the switching frequency is limited at both the upper and lower frequency range. Because the bandwidth for the subwoofer amplifier in particular is very low, the "10 times bandwidth" requirement can easily be met. Therefore, the output filter size will dominate the switching frequency selection.
For determining the die size of the switching devices, a trade-off between switching loss (increasing with die size) and conduction loss (decreasing with die size) has to be made. For Class D applications in particular, where fast switching transients are preferred for better THD, the optimum die size tends to be larger than for switching-mode power supplies (S) of similar power levels.
For the subwoofer design, the switching frequency is lower than for full bandwidth amplifiers and the optimum die size tend to be even larger. (For a more complete discussion on choosing the right switching devices, please refer to Application Note AN-1070 [Reference 2].)
For this subwoofer design, the following devices were selected for each switching device: three IRFB41N15Ds in parallel, rated at 150V(BR)DSS.
The second step is to design the output filter. The switching frequency will determine the filter corner frequency. In this case, a switching frequency of 140 kHz is chosen. This frequency is high enough to significantly reduce the size of the output filter, while low enough to limit switching losses. A fourth order output filter is chosen to achieve a sharp frequency roll off. The characteristic filter impedance is directly related to the speaker impedance, with additional damping required through a Zobel network to improve response for higher impedance speaker loads.
However, since the subwoofer bandwidth is significantly lower than the filter bandwidth, the filter requirements in this case are relaxed. The resultant Bode plot for the output filter (Figure 6b, third image below) is shown in Figure 2, immediately below. To avoid saturation under normal operation, all filter inductors should be current rated in excess of the peak current value calculated in Equation 2, in this case 23A.

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Gate drive design and propagation delay variation
In general, switching timing error in the gate drive signal is the primary cause of the non linearity for a Class D amplifier. The timing error due mismatches in signal propagation causes variation in the dead-time-the most significant contribution of nonlinearity in a Class D stage. A small amount increase in the dead time (tens of nano-seconds) can easily generate more than 1% of THD [Reference 1].
On the other hand, if the dead time is decreased beyond a certain point (depending on the switching speed of the MOSFETS), then both devices are conducting at the same time-which leads to large shoot-through currents that can, at the very least, reduce efficiency and, worse, result in device destruction. The minimum amount of dead time that can be set in production will depend on the worst case mismatch on the propagation delays between the two gate drive signals from the point where the control signal splits (considering component tolerances and part-to-part variation). Add to this the fact that the total gate charge (for the three devices in parallel) is over 240 nC, thus requiring a high (sink/source) current gate drive with accurate timing.
Furthermore, a floating (isolated) gate drive (both supply and control signal) is required for the top MOSFET (high side). Thus the high-side gate drive signal propagation has to be matched with that of the low side (where no isolation is needed). The IR2010S gate drive IC is selected at it matches these vital requirements:
Delay matching of outputs to within 15 ns
A 3A sink/source current capability
Floating high side output for up to 200V isolation
(For more complete information of gate drive ICs refer to Application Note AN-978 [Reference 3].)
The IR2010S is a high-and low-side driver with separate logic input for each of the two gate drivers (HO and LO) and requires external dead time creation. This is done through a simple edge dependent RC delay circuit as shown in the final design schematic, Fig. 6a immediately below.

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The high side gate drive needs a bootstrap power supply. A bootstrap supply is implemented simply by adding a diode between the low-side and high-side supplies. The high-side bus capacitance is recharged every time the low side MOSFET is on, while the floating bus capacitor must supply the high side current during high side MOSFET conduction. The size of this bus capacitor is, therefore, determined by the total maximum on-time of the high-side MOSFET and the allowable voltage ripple on the capacitor. The worst case would be during clipping of the output voltage when the output is over-modulated (such as at 10% THD). For a low frequency fundamental, this on-time could be tens of milliseconds, resulting in the need for a large (100 μF) bus capacitor. (Please refer to Reference 3 for more on bootstrap supply design.)
With the gate drive selected, the heart of the Class D amplifier is complete. At the input side is a PWM logic signal, while at the output, this signal is amplified into a large PWM modulated square wave voltage, where the carrier frequency is filtered out. The final step is to create a control loop with feedback and compensation to connect the output of the preamp to the Class D amplifier. Lastly, the control loop output has to be "quantized" to generate the required PWM signal (see Figure 1).
Pre amplifier design
This falls outside the scope of the Class D amplifier design, but is noteworthy. As it is easier to achieve voltage gain with good THD performance in the preamp than in the class D power stage, it is advisable to limit the voltage gain of the power stage by increasing the preamp gain.
There are wide selections of control/feedback methods available for Class D amplifiers. For this subwoofer design, a self-oscillating type PWM modulator is selected. This topology is basically an analog version of a 2nd-order sigma-delta modulation with a Class-D switching-stage inside the loop. The benefit of the sigma-delta modulation in comparison to the carrier-signal based modulator is that all the error in the audible frequency range is shifted away into the inaudible upper-frequency range by nature of its operation, and it can apply a sufficient amount of correction. A block diagram of the PWM modulator is shown in Figure 3 below.

The switch node voltage and pre-amp output is compared and the error signal is integrated. This analog error signal is then "quantized" through a comparator to generate the PWM signal. The digitized PWM signal is level shifted down to the negative bus rail (-B) where additional dead time is added and the PWM signal is split into two separate gating signals (for upper and lower MOSFETs respectively).
The main limitation of this control method is that the switching frequency does change with duty cycle. This can however be improved through the addition of an external clock for synchronization. Furthermore, having only fed back the switch node voltage and not the speaker terminal voltage, the output filter design will directly impact the THD and damping ratio of the amplifier. On the other hand, a very good power supply rejection ratio (PSRR) can be achieved with this method, which can simplify the power supply design significantly. The PSRR for this Class D amplifier is shown here in Figure 4.

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Circuit protection For the protection circuits, the main focus is simplicity and cost. The resultant protection circuits are shown in Figure 5 here.

The most important of these are the over current-protection (OCP). For a half-bridge Class D amplifier, energy flow is bidirectional and requires separate OCP for each switch. In this design, it is implemented through two shunts connected between the supplies and the MOSFETs. The OCP is latched for this single channel design, while over temperature protection (OTP) is not and will recover once the temperature has dropped sufficiently. For DC voltage speaker protection (DCP), a complete shut down of the power supplies are required, at this can only be caused by a failure of one of the MOSFETs.
Summary We have covered some of the most important aspects of a Class D subwoofer design and presented the basic design procedure for a 500W, 2Ω 500W Class D automotive subwoofer amplifier. For this power level a high current, delay-matched gate driver such as the IR2010S is required. For lower power applications, alternative ICs, such as the IRS20124S and IRS20954S with integrated over current protection, dead time generation, and comparator input are also available.
Johan Strydom is an IC systems engineer and Jun Honda is a senior IC systems engineer at International Rectifier.
References:
[1] Application Note AN-1071, "Class D Audio Amplifier Basics" [2] Application Note AN-1070, "Class D Amplifier Performance Relationship to MOSFET Parameters" [3] Application Note AN-978, "HV Floating MOS-Gate Driver ICs"